Euro-Dac '96 With Euro-Vhdl '96

Proceedings of the September 1996 conference. Contains papers in sessions on analog and mixed mode simulation, low power synthesis, design experience, timing modeling, design flow and management, partitioning, logic and FSM synthesis, BDD optimization, codesign approaches, testing, CAD of Microsystems, timing issues in synthesis, physical design for deep submicron, CAD for analog circuit, formal analysis of VHDL designs, and VHDL and mixed signal design. No index. Annotation c. by Book News, Inc., Portland, Or.